The present invention relates to semiconductor devices, and particularly to memory cells and semiconductor memory devices using the same.
Static random access memory (SRAM) integrated circuits have become popular in recent years with the advent of high speed and high density complementary metal-oxide-semiconductor (CMOS) technology. Complementary metal-oxide-semiconductor (CMOS) technology is the dominant technology currently in manufacture of ultra-large scale integrated (ULSI) circuits today. Size reduction of the semiconductor structures has provided significant improvements in speed, performance, circuit density and cost per unit function of semiconductor chips over the past few decades. Significant challenges, however, are faced as the size of CMOS devices continues to decrease.
For example, embedded SRAM is very important for high speed, low power, and system-on-chip products. In nanometer generation, each product may have several SRAM arrays on one chip. In order to improve layout efficiency and chip size and to increase chip speed, metal layer signal lines upon SRAM cell for data commutation and cross-array control lines are allowed, noise interference, however, may occur accordingly. Optimization of layout efficiency, speed, noise shielding and cell stability continues to be important. Thus, there is a need for an integrated circuit that allows signal lines through cell arrays, while providing optimum noise shielding.